The present invention relates generally to the field of semiconductors, and more specifically to the feed-forward control of a semiconductor manufacturing process.
Imaging processes for the production of micro-electronic devices on semiconductor substrates are well known in the art. Such processes generally involve the creation of a patterned layer of material for selectively exposing or protecting areas of a semiconductor substrate during a subsequent additive or subtractive process.
Photoresist compositions are widely used to form the patterned layer of material on a semiconductor substrate. A thin layer of photoresist material is first deposited on the substrate, then exposed to a controlled pattern of radiation to cause a chemical reaction in the exposed areas. Visible light, ultraviolet radiation, electron beam or X-ray energy may be used as the developing energy depending upon the photoresist material selected. The photoresist layer is then contacted with a developer solution to dissolve and to remove either the radiation exposed areas or the radiation shielded areas, depending upon the chemistry used for a particular application. If the exposed area becomes less soluble in the developer solution, the pattern remaining on the substrate is a negative image of the pattern of radiation, therefore being referred to as a negative working photoresist. If the exposed area becomes more soluble in the developer solution, the pattern remaining on the substrate is a positive image of the pattern of radiation, therefore being referred to as a positive working photoresist. In either case, a desired portion of the underlying substrate is uncovered and exposed to subsequent processing steps, while the covered portion of the underlying substrate is protected from such subsequent processing steps.
The size of semiconductor devices continues to decrease and the metrology used to measure such devices is responding accordingly. There are many types of both optical and electron based metrology tools available. As the size of devices has decreased, optical metrology for critical dimensions has been abandoned. The scanning electron microscope (SEM) currently plays a major role for metrology in the semiconductor manufacturing industry. Modem 157 nm lithography technology pushes the limits of top down critical dimension scanning electron microscopes (CDSEM). The technology critical dimension nodes of 120 nm and 100 nm lithography will require more precision and accuracy than the SEM appears to be able to provide.
Multiple parameter characterization (MPC) refers to the use of functions or groups of measurements where a singular discrete measurement can no longer effectively represent the data. MPC is being developed in many different forms for application to scanning electron microscope data in an attempt to address the shortcomings of single parameter characterization. It is known to process the output of a scanning electron microscope to generate an amplitude modulated waveform P(x) representing the intensity of reflected energy across the plane of a substrate surface. The shape and scale of the amplitude modulated waveform can be described through multiple parameters. FIG. 1 illustrates an amplitude modulated waveform P(x) as may be derived by scanning a substrate having a trench feature. The waveform of FIG. 1 is divided into two portions. The distance between the left and right regions of the waveform in solid lines defines a width measurement W and the distance between the left and right regions of the waveform in dashed lines defines a line space measurement S. At discrete intervals along the height of these regions a measurement may be taken for the width and line space, then plotted as a function of height, as shown in FIG. 2. Curve WN-SN may represent the MPC of a normal morphology. Curve WA-SA may represent the MPC of an abnormal morphology. The use of multiple parameter characterization facilitates the use of SEM data to distinguish between such normal and an abnormal morphologies.
Current micro-electronics manufacturing methods incorporate metrology for the purpose of downstream quality control. For example, once a photoresist process has been completed, it is known to utilize a scanning electron microscope or other metrology technique to measure how closely the photoresist mask corresponds to its intended configuration. A go/no-go parameter may be established, and semiconductor wafers having photoresist patterns that are outside of the acceptance limits are removed from the production line for subsequent rework. Wafers having acceptable photoresist masks are then processed through a further manufacturing step, such as for example, an etching process. A second metrology step may then be used to confirm that the resulting hard mask product falls within predetermined acceptance limits.
In spite of the numerous advances in micro-electronics manufacturing techniques, there remain many aspects of various processes that are not fully understood by those skilled in the art. The control of many micro-electronics manufacturing techniques includes a significant amount of uncertainty. Plasma etch processes are generally difficult to control, with variations occurring from wafer to wafer and from lot to lot. Uncertainties may be induced by machine aging and cleaning lead times, run-to-run variations in wafer attributes, and chemistry of the plasma. Quality control is essentially a feed-back process, i.e. the output product is measured to determine if it is acceptable, and if it is unacceptable, a control parameter is changed. The output product is then again measured to see if the desired corrective effect has been achieved. This cycle is repeated until an acceptable output product is achieved. Each step in the manufacturing process is controlled in a similar manner. For example, to achieve a desired etch pattern, there must first be a photoresist development step then an etching step. Current quality control processes involve a first metrology step on the developed photoresist pattern, then a second metrology step on the etched wafer surface. Each of these steps are treated separately, and each has its own range of acceptable variation from the ideal design value. Because these processes are both complicated and not fully understood, there has been no effort in the industry to integrate the quality control aspects of the overall manufacturing process. Such a control scheme is naturally rigid, allows for the build-up of unfavorable tolerances, and provides no capacity for accommodating deficiencies in one process with counterbalancing variations in another process.
It is known to apply a neural network to the control of a semiconductor wafer etching process. Both U.S. Pat. No. 5,653,894 issued to Ibbotson, et al., and U.S. Pat. No. 5,737,496 issued to Frye, et al, describe the use of neural networks to control the endpoint in a plasma etch process. While such systems provide a degree of in-process control for an etch process, further improvements are desired.
Thus there is a particular need for a system of process control that provides improved flexibility in the control of complex and sometimes poorly understood manufacturing processes such as are utilized for the micro-electronics industry.
Accordingly, a method of processing a semiconductor wafer is described herein as including: forming a layer on a surface of a semiconductor wafer; obtaining dimensional information describing a first feature on the layer; developing a multiple parameter characterization of the first feature from the first feature dimensional information; and providing the multiple parameter characterization of the first feature as an input to a process control neural network to identify a first process control parameter useful for controlling a process to develop a design feature having predetermined dimensions from the first feature. The method may further include: using the first process control parameter while applying the process to the semiconductor wafer to develop an actual feature from the first feature; obtaining dimensional information describing the actual feature; developing a multiple parameter characterization of the actual feature from the actual feature dimensional information; providing the multiple parameter characterization of the actual feature as an input to a training neural network to identify a second process control parameter useful for controlling the process to develop the actual feature from the first feature; comparing the first process control parameter and the second process control parameter to develop an error parameter; and using the error parameter to train at least one of the process control neural network and the training neural network. The method may further include: providing a quality control neural network to define a mapping between the multiple parameter characterization of the first feature and a representation of goodness of a lithography process used to produce the first feature; and using the quality control neural network as a filter for deciding if a semiconductor wafer should be processed through an etching process to develop the design feature.
In a further embodiment, a method of controlling a semiconductor device manufacturing process is described as using a process control neural network to map a relationship between a multiple parameter characterization of the topography of an in-process feature and a process control parameter value useful to control a process for developing a design feature having a predetermined topography from the in-process feature. The method may further include: using a training neural network to map a relationship between a feature topography resulting from the process and the process control parameter used to control the process; controlling the process with an actual process control parameter value output from the process control neural network to develop an actual feature topography from an actual in-process feature topography; developing a multi parameter characterization of the topography of the actual feature topography; applying the training neural network to the multi parameter characterization of the actual feature topography to define an ideal process control parameter value; comparing the ideal process control parameter value and the actual process control parameter to identify an error parameter; and using the error parameter to train the process control neural network.
A system for semiconductor device manufacturing is described herein as including: a metrology element for developing a multiple parameter characterization describing an in-process feature on a semiconductor substrate; a process control neural network having the in-process feature multiple parameter characterization as an input and having an estimated process control parameter value as an output; and a processing element having the estimated process control parameter value as an input for performing a process on the semiconductor substrate to develop a final feature on the semiconductor substrate. The system may further include: a metrology element for developing a multiple parameter characterization describing the final feature; a training neural network having the final feature multiple parameter characterization as an input and having an ideal process control parameter value as an output; and a comparator having the estimated process control parameter value and the ideal process control parameter value as inputs and having an error parameter as an output. At least one of the process control neural network and the training neural network may have the error parameter as an input. The system may further include a quality control neural network having the in-process feature multiple parameter characterization as an input and having a quality indicator as an output.
In a further embodiment, a system for control of a semiconductor manufacturing operation is described as including: a process control neural network having as an input a characterization of a semiconductor wafer feature prior to processing and having as an output a control parameter value for controlling a manufacturing process, the process control neural network adapted find a mapping from the pre-processing characterization to an estimated control parameter value predicted to achieve a design semiconductor wafer feature after processing; a training neural network having as an input a characterization of an actual semiconductor wafer feature after processing through the manufacturing process controlled by the estimated control parameter and having as an output an ideal control parameter value for achieving the actual semiconductor wafer feature; and a comparator for comparing the estimated control parameter value and the ideal control parameter value to generate an error parameter. The system may further include an algorithm for training at least one of the process control neural network and the training neural network, the algorithm having the error parameter as an input.